This is the second installment in a two part article about Willamette, the next generation x86 processor design from Intel. In the first part the technical and historical context of Willamette was presented along with how it differs from current Intel x86 processors. In this second part I’ll examine two of Willamette’s defining features – its trace cache and its double frequency arithmetic logic units (ALUs) in detail on the basis of available information and estimate their likely impact on Willamette’s performance.
Peering Behind the Veil of Secrecy
When it comes to revealing information about a new mainstream microprocessor that is nearly a year away from volume production, Intel Corporation is usually about as forthcoming as the U.S. National Security Agency. However, these are strange and unsettling times for Intel as it is faced with a competitor, Advanced Micro Devices (AMD), offering a product for the expansive and lucrative mainstream x86 PC market that is at least the technical match of Intel’s best. Worse still for Intel, AMD appears to be able to manufacture this processor, the K7 Athlon, at clock frequencies and in quantities to match its rapidly growing market acceptance, while Intel suffers prolonged and highly publicized difficulties in ramping the frequency and production volume of its Coppermine Pentium III.
Because of the unusual competitive situation it finds itself in, Intel is under a lot of pressure to release details about its upcoming Willamette processor far in advance of its availability. At the recent Intel Developers Forum, Intel publicly demonstrated prototype Willamette devices operating at clock rates up to 1.5 GHz. Furthermore, it revealed that the integer arithmetic logic units (ALUs) in the Willamette operated at twice the processor frequency, or up to 3 GHz. These eye-popping frequencies generated a lot of ink within the technical press and helped divert attention from the fact that Intel was losing the race to ship standard product offerings at clock rates up to 1 GHz.
The description of Willamette that follows is based on a mixture of limited architectural disclosures by Intel, several U.S. patents recently issued to Intel that apparently relate to technology used within Willamette (namely 6,018,786 and 6,023,182), and a lot of speculation. In many cases I will propose possible design approaches to specific Willamette features where the actual details are unavailable. With any complex exercise in speculation it is inevitable that errors, false trails and red herrings will creep in. Even apparently concrete details from Intel’s statements or patents shouldn’t be taken as gospel as it quite possible (and even likely) that Intel has employed some degree of misinformation to try to conceal detailed operational characteristics, manufacturing costs, and performance levels of Willamette from its competitors.
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