This is the first installment in a two-part article about Willamette, the next generation x86 processor design from Intel. It includes a description of the development roots of Willamette and the basics of how its organization and operation differs from earlier P6 generation processors. In a future article I will examine the new technology and features of Willamette in more detail and speculate on its implementation, operational characteristics, and performance.
Intel Drops Its Sledgehammer
Willamette is the code name for a new high-end x86 microprocessor core Intel will introduce towards the end of the year. Willamette is quite an interesting processor for many different reasons, both technical and historical. It is the first entirely new x86 processor design Intel has come up with since the powerful and versatile “P6” processor core was introduced in the Pentium Pro in 1995. Willamette is also the processor that Intel originally thought it wouldn’t need nearly as badly as it obviously does today. To fully understand this tangled tale we have to go back to seven years ago when computer users frustrated with their 486DX2 systems were eagerly awaiting a new Intel processor with a funny name instead of a number.
In early 1993 Intel’s Santa Clara processor design team had just finished off the P5 project (Pentium) and started work on the P7. Intel had initiated a new strategy to operate two separate x86 processor development teams in parallel, in an overlapped fashion. Under this strategy, when the first team finishes the generation N processor design it starts work on the generation N+2 processor, while the second team is in the middle of the generation N+1 processor project. The hope was to cut the four-year intervals between new processor cores in half. When work on the P7 started up in Santa Clara, Intel’s P6 team in Hillsboro Oregon was about 18 months and a lot of hard work away from delivering the Pentium Pro. The P7 was a powerful 64-bit x86 compatible successor to the P6 envisioned to have around 20 million transistors or nearly four times as many as the Pentium Pro. In some ways Intel’s original P7 project conceptually resembles AMD’s K8 “sledgehammer”, the 64-bit successor to the K7 Athlon.
The P7 progressed only far along enough for Intel’s engineers to realize that extending x86 to 64 bits, and staying competitive with RISC processors, would be challenging to say the least. Around this time Intel entered into an alliance with Hewlett Packard to develop a high performance 64-bit processor incorporating variable length VLIW technology from HP’s “Wide word” extension to its Precision Architecture RISC architecture. In 1994 the Santa Clara team dropped all work on the 64 bit x86 processor design called P7 and started on the first implementation of the new IA-64 architecture arising from the Intel-HP alliance, a processor later known as Merced. The Merced project adopted the P7 designation, and its troubled offspring is targeted to reach the market later this year under the name “Itanium”.
By 1996 the P6-based Pentium Pro was shipping and plans were made to create high volume consumer versions of the P6 core. Also around this time Intel was touting the new P7 (Merced) with its dual x86 and IA-64 capability as the next generation Intel processor. Unfortunately for Intel, the development of Merced and its successors proved more difficult and time consuming than originally thought and the IA-64 deployment schedule started to slip, first by months, and then by years. Even as late as 1996 Intel publicly proclaimed that Merced would ship in volume in 1998.
Waiting for no project, Moore’s Law inexorably pushed semiconductor technology forward and dragged along P6 based designs to ever higher levels of performance. Since Merced wasn’t getting any faster as its schedule slipped, its performance on x86 code was starting to look weaker and weaker compared to the P6 designs it was supposed to replace. This relative slippage is reflected in a succession of public pronouncements about Merced’s x86 performance from being the fastest x86 processor to being equivalent to a mid range x86 MPU. At the same time competition in the x86 market was starting to heat up with the introduction of the AMD K6, and the announcement of the K7 development project and its licensed use of Alpha EV6 bus technology.
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