x86 Servers Brace for a Hurricane

Pages: 1 2 3 4 5 6 7 8

Building Blocks

The vast majority of x86 server vendors use Intel’s standard chipset. This certainly is a blessing for white box vendors, who cannot afford their own R&D, and other vendors such as Dell, that choose to forego the associated costs. However, to IBM this represents an opportunity to use their big system expertise to create a more scalable solution. This tactic reflects IBM’s general strategy. IBM tends to favor markets where they can leverage their talents and command a premium over competitive offerings, and shun highly competitive, price sensitive markets (such as PCs).

The XA-64e or “Hurricane” chipset is IBM’s next-generation x86 chipset, and is designed to scale from simple uniprocessor servers and workstations to 64P systems with dual core MPUs. Since there are few large x86 servers; notably Unisys’ ES7000 and IBM’s xSeries, it is somewhat difficult to find a point of comparison for the X3 architecture. As Dr. Bradicich noted in his talk, the most natural point of comparison to the X3 is its predecessor, the EXA2 chipset, since IBM has a wealth of information on both. The X3 represents a significant improvement over the prior generation chipset, supporting dual 667MHz front-side buses, snoop filtering, on-chip directory based coherency, virtual caching, PCI-X 2.0 and DDR2 memory.

Like most large systems, the X3 uses small 4P (8P with dual-core) building blocks and connects them together to build larger systems. Each quad contains local memory, I/O, a snoop filter and an on-chip directory. Up to eight quads can be connected together, to form a 32P system (or 64P with dual core chips). A single quad is depicted below in Figure 1:

Figure 1 – Single Quad for the X3 Chipset, based on an IBM presentation

The X3 architecture was announced on February 22, 2005 and the eServer x366 has been available since March 29. The x366 uses Intel’s Xeon MP chips [3]. Initial benchmarks released for this system use the Cranford model Xeon MPs (3.66GHz, 1MB L2 cache). IBM has submitted two sets of 4P TPC-C results; one using MS SQL and one using IBM’s own DB2. Unsurprisingly, the DB2 based system slightly edges out the MS SQL system by around 9K TpmC (141K vs. 150K) [3].

Pages: « Prev   1 2 3 4 5 6 7 8   Next »

Discuss (13 comments)