Update to Intel Optimization Manual

By: SHK (no.delete@this.mail.com),
Room: Moderated Discussions
Finally Intel has released the new updated version (-031) of the Optimization Manual:
http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf

There're some new details on Skylake:

* Front end now has 5 decoders from the usual 4.
* Micro-ops cache can deliver 6 m-ops/cycle instead of 4.
* loop-buffer size is now 64 m-ops
* bigger OoO structures (but no official numbers cited, IIRC ROB size is 224 entries, RS size is 97)
* page split load penalities from 100 cycles to 5 (that's an improvement!)
* longer idle time for the PAUSE instruction
* faster L3, 2-cycles per line now

That's what i've noticed from a fast browsing, i have yet have to dig into instruction latency tables.
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Thread (91 posts)
TopicPosted ByPosted
Update to Intel Optimization ManualSHK
  gather speedEric Bron
    gather speedGabriele Svelto
  Update to Intel Optimization ManualTim McCaffrey
    Update to Intel Optimization ManualSHK
      Update to Intel Optimization ManualAnon
    Update to Intel Optimization Manualnone
      Update to Intel Optimization ManualMichael S
    Update to Intel Optimization ManualMichael S
      Update to Intel Optimization ManualTim McCaffrey
  5-6 wide core, why no mention from Intel?Wouter Tinus
    5-6 wide core, why no mention from Intel?Maynard Handley
      5-6 wide core, why no mention from Intel?Alberto
        5-6 wide core, why no mention from Intel?anon
          5-6 wide core, why no mention from Intel?Alberto
            5-6 wide core, why no mention from Intel?anon
              5-6 wide core, why no mention from Intel?Alberto
                5-6 wide core, why no mention from Intel?juanrga
        5-6 wide core, why no mention from Intel?Maynard Handley
    5-6 wide core, why no mention from Intel?juanrga
      5-6 wide core, why no mention from Intel?Wouter Tinus
        5-6 wide core, why no mention from Intel?juanrga
          5-6 wide core, why no mention from Intel?Wouter Tinus
            Are you kidding? (NT)juanrga
              Are you kidding?Wouter Tinus
                Are you kidding?juanrga
                  Are you kidding?David Kanter
                    Are you kidding?anon
                    Are you kidding?Linus Torvalds
                      Are you kidding?juanrga
                        Are you kidding?anon
                  Are you kidding?Wouter Tinus
                    Are you kidding?juanrga
                      Are you kidding?Stubabe
                        Are you kidding?juanrga
                          Amazing...Wouter Tinus
                            Amazing...juanrga
                          Are you kidding?Stubabe
                            Are you kidding?juanrga
                          Are you kidding?Wilco
                            Are you kidding?juanrga
      5-6 wide core, why no mention from Intel?Eric Bron
    5-6 wide core, why no mention from Intel?David Kanter
      Optimal number and kind of execution unitsjuanrga
        Optimal number and kind of execution unitsPatrick Chase
          Optimal number and kind of execution unitsI.S.T.
            Optimal number and kind of execution unitsPatrick Chase
          Optimal number and kind of execution unitsExophase
          Optimal number and kind of execution unitsjuanrga
      LD/ST unitsSHK
        LD/ST unitsDavid Kanter
          LD/ST unitsSHK
            LD/ST unitsJukka Larja
        LD/ST unitsMaynard Handley
          LD/ST unitsanon
      5-6 wide core, why no mention from Intel?Maynard Handley
        5-6 wide core, why no mention from Intel?David Kanter
          5-6 wide core, why no mention from Intel?Maynard Handley
          5-6 wide core, why no mention from Intel?Exophase
            5-6 wide core, why no mention from Intel?Maynard Handley
              5-6 wide core, why no mention from Intel?Megol
                5-6 wide core, why no mention from Intel?Michael S
                5-6 wide core, why no mention from Intel?Maynard Handley
                  5-6 wide core, why no mention from Intel?noko
              5-6 wide core, why no mention from Intel?Exophase
                5-6 wide core, why no mention from Intel?Maynard Handley
                  5-6 wide core, why no mention from Intel?Exophase
          5-6 wide core, why no mention from Intel?Wilco
            5-6 wide core, why no mention from Intel?Maynard Handley
              5-6 wide core, why no mention from Intel?Wilco
              5-6 wide core, why no mention from Intel?noko
                5-6 wide core, why no mention from Intel?Maynard Handley
            5-6 wide core, why no mention from Intel?David Kanter
              5-6 wide core, why no mention from Intel?Wilco
                5-6 wide core, why no mention from Intel?David Kanter
                  5-6 wide core, why no mention from Intel?Wilco
                    LDP/STP usage in AArch64 for 403.gccnone
                      LDP/STP usage in AArch64 for 403.gccWilco
                        LDP/STP usage in AArch64 for 403.gccnone
                          LDP/STP usage in AArch64 for 403.gccWilco
                            LDP/STP usage in AArch64 for 403.gccnone
                              LDP/STP usage in AArch64 for 403.gccWilco
                  5-6 wide core, why no mention from Intel?Maynard Handley
              5-6 wide core, why no mention from Intel?Maynard Handley
  Update to Intel Optimization Manualanon
  Update to Intel Optimization ManualPatrick Chase
    Update to Intel Optimization Manualanon
    Update to Intel Optimization Manualnone
    Update to Intel Optimization ManualDavid Kanter
      Update to Intel Optimization ManualPatrick Chase
        Update to Intel Optimization Manualanon