More Interconnect Tricks
The last, and most commonly used, method of mitigating the interconnect problem has been to add additional layers  of metal to the interconnect stack per process contraction, as shown in Figure 3. Note that in Figure 3, the even numbered metal layers run horizontally across the image, while odd numbered layers run perpendicular to the image. More metal wires increase active power consumption however, as greater signal transitions occur. More importantly additional metal layers require extra processing steps on the wafers, which increase the fabrication costs. Extra processing steps also reduce yields – the number of good die per wafer – as bonding extra metal layers increases wafer defect rate, which in turn drives up overall cost for the end product. The new interconnect layers are usually inserted at the bottom, nearest to the functional unit blocks at the local level, with dimensions shrunk to match the scaling of the transistors.
Figure 3 – Interconnect scaling with additional metal layers M1 and M2 added at bottom
Metal layers are deposited one at a time on top of the silicon substrate. The size and cross-sectional area of each layer of metals increases on each layer. The global wires, which are the highest, are the thickest and therefore have the least resistance and latency per unit length. Of course these highest quality wires must travel the farthest as they are used to distribute the global clock and power to the functional unit blocks. Since new finer metal layers are added at the bottom, the upper metal layers generally keep their dimensions and spacing between their constituent wires from the last process generation. As a result, the latency characteristics of the global wires are the same as for the prior generation process.
Figure 4 – 130nm process generation with 6 layers of copper interconnect (Source: Intel)
Unfortunately adding more metal layers is still not enough to appreciably ameliorate the growing mismatch in performance between transistors and global interconnect. The amount of global interconnect on die remains constant while the number of transistors doubles per generation. In some cases global wires can be moved further apart from one another, which reduces the parasitic capacitance and increases signal propagation performance. However this significantly decreases global metal density, whereas transistors are always getting denser with each process generation. The effect of this is that chips are made unnecessarily larger in size to accommodate global interconnect. The separation between the functional unit blocks and the intermediate wires above will grow, analogous to suburban sprawl, diminishing transistor density and negatively affecting Moore’s Law. To a certain degree this is occurring now with increasingly interconnect constrained designs.
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