3D Manufacturing Options
The most promising vertical interconnect strategies involve through die vias, particularly through silicon vias, which promise the highest vertical interconnect density. Vias are the short vertical wires between layers of interconnect, connecting planar wires. Figure 8 below shows a variety of vias from a scanning electron microscope.
Figure 8 – (a) Cross section of ~1.6um high via, (b) cleaved SEM image of isolated via (c), cleaved SEM image of ~175nm diameter vias (Source: IBM)
There are two primary methods of manufacturing three dimensional chips [10]. The ‘bottom up’ wafer fabrication method builds silicon layers sequentially on top of each other. The first layer is formed and transistor devices are fabricated, followed by the deposition of the second layer and the subsequent fabrication of its devices. This method requires substantial changes to the manufacturing process. There are also quality concerns regarding the device reliability fabricated in subsequent layers deposited on top of the earlier ones. One advantage of this method is that the size of the inter-layer vias can scale down with the transistor devices.
On the other hand, the ‘top down’ wafer fabrication method manufactures each layer separately and afterwards bonds them together. This is a more popular method for several reasons. Each wafer layer is qualified separately, and if a wafer meets quality criteria, it can then be assembled together with another already qualified wafer. Another advantage is that heterogeneous silicon layers, each one optimized for separate process functions, can be combined together. For example, one layer could be designed for memory density, while another is targeted at logic performance. One notable drawback of the ‘top down’ method is that the size of the inter-layer vias is not expected to scale at the same rate as the transistor devices. Even in the best case, vias cannot decrease below one micrometer in width, because of inter-inter layer bonding alignment tolerances. However this fabrication method requires the least amount of changes to existing processes, minimally perturbing manufacturing costs.
In the top down method, wafers and dies can be bonded face to face, or face to back. In the straightforward face to face bonding method, the tops of two layers are stacked facing each other, with their interconnect layers exposed and connected by vias. This results in the smallest possible inter-layer distance and hence smaller via sizes. In the more general face to back bonding approach, each layer is stacked on top of another, all having the same orientation. The distance between layers is larger and the vias must be larger as they have to go through the silicon substrate of each layer, forming a direct vertical interconnection. The wafer layers can be thinned, achieving better electrical characteristics and control.
The thicker vias do take away surface area from transistors. However this is not expected to be a problem, since transistors in current designs are not arranged densely due to global interconnect issues. The transistors could be densely arranged around the vias to form islands of logic. For three dimensional stacking with more than two layers, face to back bonding is the only viable approach in unlocking the true promise and full benefits of the third dimension.
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