I have had trouble finding this information first-hand, I wonder if anybody here can help. L1 data cache error protection. This seems to not use ECC but parity protection in mainstream Intel cores including Xeon, despite being a writeback cache. Some E7 Xeons at one time or another seem to have been able to run in an ECC protected mode at half capacity. I can find very little data about that, or what recent cores do, which is the only reason why I presume they still don't ECC protect (otherwise they would be advertising it).