By: slacker (s.delete@this.lack.er),
Room: Moderated Discussions
Michael S (already5chosen.delete@this.yahoo.com) on March 15, 2017 4:19 pm wrote:
> slacker (s.delete@this.lack.er) on March 15, 2017 2:59 pm wrote:
> >
> > The emperor has no clothes; I suspect AMD is literally using PCIe as an interprocessor interconnect, with a
> > cHT protocol layered on top.
>
> Why do you suppose so?
> It seems to me, it is technically possible to use the same electrical drivers/receivers
> for both PCIe or HT3. In FPGAs they are doing it routinely for as long as they
> started to support differential I/O at PCIe Gen2 or higher speed.
I considered that, but is AMD willing to implement two controllers (PCIe + HT) on each Naples chip, and then share the transceivers (and maybe the serdes blocks)? The PCIe controllers and switches for half the PCIe lanes (64x) will be sitting unused.
> slacker (s.delete@this.lack.er) on March 15, 2017 2:59 pm wrote:
> >
> > The emperor has no clothes; I suspect AMD is literally using PCIe as an interprocessor interconnect, with a
> > cHT protocol layered on top.
>
> Why do you suppose so?
> It seems to me, it is technically possible to use the same electrical drivers/receivers
> for both PCIe or HT3. In FPGAs they are doing it routinely for as long as they
> started to support differential I/O at PCIe Gen2 or higher speed.
I considered that, but is AMD willing to implement two controllers (PCIe + HT) on each Naples chip, and then share the transceivers (and maybe the serdes blocks)? The PCIe controllers and switches for half the PCIe lanes (64x) will be sitting unused.
