By: Aaron Spink (aaronspink.delete@this.notearthlink.net),
Room: Moderated Discussions
Ricardo B (ricardo.b.delete@this.xxxxx.xx) on March 16, 2017 5:30 am wrote:
>
> Yes, at the physical layer they need to be similar enough to share the same I/O cells.
> Which means some sort of differential current mode signaling, which is the case.
>
> But beyond that, there's considerable freedom, as long as you can afford the die space.
> Eg, after the input cells, you can feed the signals to otherwise distinct:
> a) Infitiny Fabric (IF) input blocks
> b) PCIe input blocks
>
> No need for IF to be multi-lane serial, which in my definition of multi-lane serial implies a pretty
> long RX/TX pipeline (serializer/deserializer, 64B/66B encoder/decoder, FIFO, lane matching logic).
>
>
Things like SERDES, encoding, fifo, etc are pretty fundamental to the I/O cells. From both a layout/logic perspective and even more importantly from an electrical perspective.
>
> Yes, at the physical layer they need to be similar enough to share the same I/O cells.
> Which means some sort of differential current mode signaling, which is the case.
>
> But beyond that, there's considerable freedom, as long as you can afford the die space.
> Eg, after the input cells, you can feed the signals to otherwise distinct:
> a) Infitiny Fabric (IF) input blocks
> b) PCIe input blocks
>
> No need for IF to be multi-lane serial, which in my definition of multi-lane serial implies a pretty
> long RX/TX pipeline (serializer/deserializer, 64B/66B encoder/decoder, FIFO, lane matching logic).
>
>
Things like SERDES, encoding, fifo, etc are pretty fundamental to the I/O cells. From both a layout/logic perspective and even more importantly from an electrical perspective.
