By: Aaron Spink (aaronspink.delete@this.notearthlink.net),
Room: Moderated Discussions
Gabriele Svelto (gabriele.svelto.delete@this.gmail.com) on March 17, 2017 3:35 am wrote:
> Michael S (already5chosen.delete@this.yahoo.com) on March 16, 2017 2:33 pm wrote:
> > Of course, you are correct. There is only one clock pair per 20 data pairs. It's true
> > for all generations of Xeons taht I checked, from Gainstown and up to IvyBridge-EX.
>
> That is... remarkable at the GT/s they support.
The reality is that QPI is not a traditional clk_fwd design. In a lot of ways, QPI electrical is more similar to an AC coupled embedded clock system. Actually using embedded clocks has significant bandwidth/latency impacts for a cacheline interconnection network, as such, an external clock is used to remove the need for strict disparity limits and link encoding.
> Michael S (already5chosen.delete@this.yahoo.com) on March 16, 2017 2:33 pm wrote:
> > Of course, you are correct. There is only one clock pair per 20 data pairs. It's true
> > for all generations of Xeons taht I checked, from Gainstown and up to IvyBridge-EX.
>
> That is... remarkable at the GT/s they support.
The reality is that QPI is not a traditional clk_fwd design. In a lot of ways, QPI electrical is more similar to an AC coupled embedded clock system. Actually using embedded clocks has significant bandwidth/latency impacts for a cacheline interconnection network, as such, an external clock is used to remove the need for strict disparity limits and link encoding.