By: David Kanter (dkanter.delete@this.realworldtech.com),
Room: Moderated Discussions
anon (spam.delete.delete@this.this.spam.com) on September 9, 2017 6:18 am wrote:
> Domaldel (moris.b.rubeksson.delete@this.gmail.com) on September 6, 2017 7:47 pm wrote:
> > So, given what we know about Zen, what are some of the low hanging fruits that could be changed for Zen+?
> > With when Zen+ is expected to come out, the process node, and what we expect from
> > Intel, what changes would you guys make to Zen to create Zen+ do you think?
> >
> > What would be your dream additions?
> > What would be the minimum required to stay competitive?
> > And what's the low hanging fruits that you can pretty much get at no cost with Zen
> > as it is today even if you don't try to be competitive with future products?
> >
> > Is there any patents stopping AMD from achieving some of those targets you think are necessary?
> >
> > I'm looking forward to the input from you all. =)
>
> If we're talking about the "14nm+" Zen and not the 7nm Zen2 then there's a couple of things they could do.
>
> http://i.imgur.com/8Rch6JF.png
> With a little bit of tweaking + 14nm+ they can probably move the point where
> the required voltage and therefore power consumption explode to a bit higher
> frequencies. A few hundred MHz more and Zen+ should be in a very good spot.
>
> Apart from the usual bugfixes the cores will probably not change much. 256
> bit FPUs and higher cache bandwidth most likely won't happen until 7nm.
I think 256b FPUs could be feasible in the near future.
> Some tweaking for the memory controller and perhaps squeezing a bit of bandwidth/latency out of the infinity
> fabric would be nice. Because Intel's mesh design got higher latency than the previous rings the inter-CCX
> latency isn't too far off, so getting that down a bit would make it more or less competitive (lower latency
> within the CCX, slightly higher outside).
If you do the math, the mesh is actually lower latency than the ring.
> CCX with more cores would be an option but that would raise latency
> within the CCX and require more effort (and require different scheduling), so I don't think they'll do that,
> but if they can afford it I'd like to see a 4 CCX/16 core die. Considering Intel actually recommends SNC mode
> AMD would be basically up to par in terms of the number of low latency core cluster size.
What AMD really needs to do is distributed home agents. The problem is that in many cases on-die cache accesses proceed at the speed of memory due to the overall coherency system and specifically the centralized home agents.
David
> Domaldel (moris.b.rubeksson.delete@this.gmail.com) on September 6, 2017 7:47 pm wrote:
> > So, given what we know about Zen, what are some of the low hanging fruits that could be changed for Zen+?
> > With when Zen+ is expected to come out, the process node, and what we expect from
> > Intel, what changes would you guys make to Zen to create Zen+ do you think?
> >
> > What would be your dream additions?
> > What would be the minimum required to stay competitive?
> > And what's the low hanging fruits that you can pretty much get at no cost with Zen
> > as it is today even if you don't try to be competitive with future products?
> >
> > Is there any patents stopping AMD from achieving some of those targets you think are necessary?
> >
> > I'm looking forward to the input from you all. =)
>
> If we're talking about the "14nm+" Zen and not the 7nm Zen2 then there's a couple of things they could do.
>
> http://i.imgur.com/8Rch6JF.png
> With a little bit of tweaking + 14nm+ they can probably move the point where
> the required voltage and therefore power consumption explode to a bit higher
> frequencies. A few hundred MHz more and Zen+ should be in a very good spot.
>
> Apart from the usual bugfixes the cores will probably not change much. 256
> bit FPUs and higher cache bandwidth most likely won't happen until 7nm.
I think 256b FPUs could be feasible in the near future.
> Some tweaking for the memory controller and perhaps squeezing a bit of bandwidth/latency out of the infinity
> fabric would be nice. Because Intel's mesh design got higher latency than the previous rings the inter-CCX
> latency isn't too far off, so getting that down a bit would make it more or less competitive (lower latency
> within the CCX, slightly higher outside).
If you do the math, the mesh is actually lower latency than the ring.
> CCX with more cores would be an option but that would raise latency
> within the CCX and require more effort (and require different scheduling), so I don't think they'll do that,
> but if they can afford it I'd like to see a 4 CCX/16 core die. Considering Intel actually recommends SNC mode
> AMD would be basically up to par in terms of the number of low latency core cluster size.
What AMD really needs to do is distributed home agents. The problem is that in many cases on-die cache accesses proceed at the speed of memory due to the overall coherency system and specifically the centralized home agents.
David