anon (anon.delete@this.anon.com) on May 17, 2018 6:44 pm wrote:
> Linus Torvalds (torvalds.delete@this.linux-foundation.org) on May 17, 2018 10:53 am wrote:
> > It's quite reliable for me:
> >
> >
> >

1k: 1.28ns (~5.0 cycles)
> > 2k: 1.28ns (~5.0 cycles)
> > 4k: 1.28ns (~5.0 cycles)
> > 8k: 1.28ns (~5.0 cycles)
> > 16k: 1.28ns (~5.0 cycles)
> > 32k: 1.31ns (~5.1 cycles)

>
> What has a 5 cycle L1d latency with simple addressing mode?
>

It doesn't have a simple addressing mode. The key line in the benchmark loop is:

offset = *(unsigned int *)(map + offset);

i.e., it will use a 2-reg addressing mode and hence get the extra cycle of latency on Intel.