The RISC-V bitmanip ISA extension has conditional moves

By: Linus Torvalds (torvalds.delete@this.linux-foundation.org),
Room: Moderated Discussions
Wilco (wilco.dijkstra.delete@this.ntlworld.com) on November 3, 2019 5:38 am wrote:
> Gabriele Svelto (gabriele.svelto.delete@this.gmail.com) on November 3, 2019 1:25 am wrote:
> > I hope that settles it since it comes up in each and every RISC-V discussion.
>
> It's just a proposal at this point. The extension is quite large and consists of several
> optional parts, so it isn't obvious whether conditional moves will ever be added. Even
> then it isn't obvious the extension will ever be used in implementations which would
> benefit the most (ie. lower-end ones with no or basic branch predictors).

That also shows the fundamental ugly side of the whole RISC-V "everything is an extension".

Many of the suggestions look very useful, but look at rotate vs shift-double ("funnel shift").

Rotate could just be implemented as a shift-double with the same value in the high/low registers.

But because of the RISC-V mentality of "everything is an extension", you can't do that, because then you wouldn't have the simpler "rotate" at all unless you had the full ternary extension.

At some point, the "RISC" part is just "UGLY".

Yes, x86 has both rotate and double shift, but at least there it's for legacy reasons, not because of a misguided "we want to intentionally fracture the ISA as much as possible, so that nobody can ever complain about the size of it".

I seriously believe that the whole mental model there is broken. It basically guarantees that there is not one RISC-V model, there are just lots of tiny fragments.

At some point the people involved should just admit that it causes more problems than it really solves.

Linus
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                  RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto
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                      RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto
                        RISC-V - incompetitive instruction set compared to ARMv8Michael S
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                        RISC-V - incompetitive instruction set compared to ARMv8David Hess
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                      RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto
                      RISC-V - incompetitive instruction set compared to ARMv8R
                RISC-V - incompetitive instruction set compared to ARMv8sylt
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            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto
              The RISC-V bitmanip ISA extension has conditional movesWilco
                The RISC-V bitmanip ISA extension has conditional movesLinus Torvalds
                The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto
                  The RISC-V bitmanip ISA extension has conditional movesnone
                    The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto
                      The RISC-V bitmanip ISA extension has conditional movesnone
                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto
                          The RISC-V bitmanip ISA extension has conditional movesnone
                            I'm glad you're not that blind :) (NT)none
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto
                          The RISC-V bitmanip ISA extension has conditional movesMaynard Handley
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto
                              The RISC-V bitmanip ISA extension has conditional movesAdrian
                                The RISC-V bitmanip ISA extension has conditional movesRonald Maas
                                  The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto
                                    The RISC-V bitmanip ISA extension has conditional movesdmcq
                                    The RISC-V bitmanip ISA extension has conditional movesKonrad Schwarz
                                      The RISC-V bitmanip ISA extension has conditional movesnone
                                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto
                      The RISC-V bitmanip ISA extension has conditional movesanon
                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto
                          The RISC-V bitmanip ISA extension has conditional movesanon
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto
                              The RISC-V bitmanip ISA extension has conditional movesnone
                                RISC-V - incompetitive instruction set compared to ARMv8Ronald Maas
                                  RISC-V - incompetitive instruction set compared to ARMv8anonymou5
                                    The RISC-V bitmanip ISA extension has conditional movesRonald Maas
                                      The RISC-V bitmanip ISA extension has conditional movesnone
                                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto
                                      The RISC-V bitmanip ISA extension has conditional movesAdrian
                                        The RISC-V bitmanip ISA extension has conditional movesAdrian
                                        The RISC-V bitmanip ISA extension has conditional movesnone
                                          The RISC-V bitmanip ISA extension has conditional movesAdrian
                                      The RISC-V bitmanip ISA extension has conditional movesdmcq
                                      The RISC-V bitmanip ISA extension has conditional movesnoko
                                        The RISC-V bitmanip ISA extension has conditional movesRonald Maas
                              The RISC-V bitmanip ISA extension has conditional movesj
                          The RISC-V bitmanip ISA extension has conditional movesdmcq
                          The RISC-V bitmanip ISA extension has conditional movesMaynard Handley
                      The RISC-V bitmanip ISA extension has conditional movesAnon
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                RISC-V - incompetitive instruction set compared to ARMv8Michael S
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