By: Clinton Ingram (clintron3000.delete.delete@this.this.gmail.com),
Room: Moderated Discussions
Andrey (andrey.semashev.delete@this.gmail.com) on March 22, 2021 4:20 am wrote:
> It would be interesting to see if Rocket Lake/Cypress Cove
> is also affected by this. I would guess, it probably is.
>
> It's also interesting how likely it is to be fixed for Alder Lake/Golden Cove. Technically,
> this is a new microarchitecture revision, but it should be at a very late stage at this
> point. I guess, it depends on how long ago Intel had discovered the defect.
>
In case anyone is wondering, mov elimination appears to be working on the Tiger Lake H revision where it wasn't working on original Tiger Lake. Results from a Mobile Xeon W-11855M
** Running group misc : Miscellaneous tests **
Benchmark Cycles Nanos
8 chained moves 2.00 0.63
8 chained movs and inc 4.66 1.46
> It would be interesting to see if Rocket Lake/Cypress Cove
> is also affected by this. I would guess, it probably is.
>
> It's also interesting how likely it is to be fixed for Alder Lake/Golden Cove. Technically,
> this is a new microarchitecture revision, but it should be at a very late stage at this
> point. I guess, it depends on how long ago Intel had discovered the defect.
>
In case anyone is wondering, mov elimination appears to be working on the Tiger Lake H revision where it wasn't working on original Tiger Lake. Results from a Mobile Xeon W-11855M
** Running group misc : Miscellaneous tests **
Benchmark Cycles Nanos
8 chained moves 2.00 0.63
8 chained movs and inc 4.66 1.46
