With all the discussions the x86 and Arm (well Apple) matrix extensions got, I thought I'd share what's going on in the RISC-V world.

As per usual everybody ended up with different usecases/targets, so there are now four+ "Matrix" extensions in the works:

batched-dot-product:
https://github.com/riscv/riscv-isa-manual/blob/zvbdot/src/zvdota.adoc
This one doesn't introduce new state and works best with the existing processor pipeline.
It has the furthest along to ratification, the spec has already been frozen.

Integrated Matrix Extension (IME):
https://github.com/riscv/integrated-matrix-extension/blob/main/src/integrated-matrix.adoc
Doesn't add new state and repurposes RVV vector registers, as matrix tiles.
The spec is currently under stabilization, but not yet frozen.

Vector Matrix Extension (VME):
https://github.com/riscv/riscv-isa-manual/blob/zvt/src/unpriv/zvt.adoc
Adds a new matrix accumulator state, but inputs to matmul operation come from the vector registers.
The spec development is somewhere between IME and AME, though closer to IME.

Attached Matrix Extension (AME):
https://github.com/riscv/riscv-attached-matrix-extension/releases/download/riscv-isa-release--2026-07-09/Ztt-0.1.pdf
All new state, for both accumulators and operands, independent of RVV and includes its own element-wise operations.
This one is still very much in draft/development state and a lot of things will change.
If you whant to have a laugh, look at Chapter 4. Datatypes.

To add more fule to the fire, there is also Zvdot4a8i: https://github.com/riscv/riscv-isa-manual/pull/2576
Which adds 4x8-bit -> 32-bit widening RVV instructions.