IEDM 2010 Process Technology Update

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TSMC’s Low Power 28nm

The last process technology update is from TSMC, presented at VLSI Symposium 2009. Paper 11A-2 describes a low power 28nm node with conventional poly-silicon transistor architecture. While a HKMG stack is clearly superior for performance sensitive applications, there are many SOCs which require only a certain level of performance and would rather minimize cost and power. Moreover, poly-silicon is also more familiar and comfortable for many analog circuit designers. For instance, most feature phones would be better suited to such a process technology. The 28nm SOC process is largely derived from TSMC’s low power 32nm process previously disclosed at IEDM 2007, with a 10% shrink.

The 28nm process has two families of transistors, one set that is tuned for low standby power (LSTP) in regions of the chip that are always active, and another optimized for low operating power (LOP). Both types of logic transistors have 117nm contacted gate pitch and use a SiON gate oxide. The LSTP devices have comparable NMOS performance to 32nm, while the PMOS has been enhanced with embedded SiGe and have roughly 20% higher performance. The LOP devices have a smaller 1.35nm gate oxide to improve switching performance and compete with alternative HKMG offerings at low voltage. At 0.8V and leakage of 100nA/um, the LOP transistors achieve saturated drive currents of 700uA/um and 400uA/um for NMOS and PMOS. While these numbers sound relatively umimpressive – recall that they are for 0.8V. Figure 8 shows the performance curves for the LOP devices at 0.8V, compared to a competing 32nm high-k/metal gate process.


Figure 8 – TSMC 28nm Low Power Transistor Performance, compared to 32nm HKMG reference

For interconnects, the 28nm process implements 10 layers of copper. TSMC also fabricated a 64Mbit SRAM array as test vehicle for ramping yields. As with most other modern process technologies, there are two SRAM cell sizes. The 0.127um2 cells are tuned for maximum density, but require 1.1V for operation. Trading off density for lower operating voltage (e.g. in SRAMs used with logic), TSMC also provides a 0.155um2 cell that requires ~0.7V.

As with other papers on SOC process technologies, TSMC highlighted the performance for various analog and RF devices. Figure 9 shows the performance for a MOS varactor.


Figure 9 – Q Factor vs. Frequency for 28nm Varactor

The overall thrust of TSMC’s presentation was that they believe they can provide excellent alternatives to a high-k/metal gate process while using a conventional gate stack for low power devices. The key was creating two families of logic transistors, and selectively optimizing one to try and match HKMG performance at low voltage, and providing a second higher voltage family with extremely low power. The net result is that TSMC claims they provide a 25-40% speed gain or 30-50% active power reduction (or some linear combination thereof) compared to their previous 45nm process.

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