For more than 40 years, competition in the computer industry has been characterized as a game of leapfrog. Major new systems take years to conceive, design, verify and put into production, while at the same time the basic electronic technology underlying computers has improved in performance and dropped in cost exponentially. Because the product cycles of different vendors are often out of phase, it is common for the performance lead to exchange hands whenever new systems are introduced. This was the case in mid-2003 when Intel introduced the Madison 6M version of the Itanium 2 processor, which quickly took the lead in most commercial and technical computing. The wheel turned quite convincingly a year later when IBM introduced its POWER5 processor. What was originally represented as basically a POWER4+ augmented with simultaneous multithreading (SMT) capabilities turned out to be effectively a top to bottom redesign with substantial improvements in both the processor and system level architecture.
Although moderate increases in commercial and throughput oriented performance was expected from the addition of SMT to POWER5, greatly improved latency and bandwidth in its cache and memory system not only amplified the increase in throughput but also raised single thread performance far above that of the POWER4+ and allowed it to take the lead in technical computing benchmarks like SPECfp2000 which the Madison I2 had previously held unchallenged. The POWER5’s margin of leadership can be expected to increase in the near future, as larger CPU count systems are gradually introduced.
But the game of leapfrog never ends. Intel’s response will come in two parts; the first is the imminent release of the Madison 9M. However, this device was originally a modest incremental improvement over the existing Madison and a recently disclosed reduction in its maximum clock rate target will reduce its impact even more. The real battle will come about a year from now when Intel introduces the Montecito, a 90nm dual core IPF processor with multithreading and massive, fast on-chip caches. This article examines the POWER5 and Montecito and describes the various ways each device is a substantial improvement over its predecessor and speculates how Montecito, the POWER5, and its anticipated 90nm shrink follow-on, POWER5+, will compare in the arena of super heavyweight class of server MPUs and systems.
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