Sizing up the Super Heavyweights

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References

[1] Kalla, R. et al, “Simultaneous Multi-threading Implementation in POWER5”, Technical Digest, Hot Chips 2003, August 2003.

[2] “POWER5 Overview”, IBM Corporation, July 13, 2004.

[3] Grassl, C., “POWER5 and HPS Programming Strategies: System Architecture”, IBM Corporation, July 2004.

[4] “IBM Deep Computing Strategy”, IBM Corporation, 2004.

[5] McNairy, C., “A Technical Review of Montecito”, Intel Developer Forum, September 2004.

[6] Otellini, P., “Growth at the Platform Level”, Intel Corporation, May 2004.

[7] Wolochow, P., “Architecting New IT Enterprise Deployment Models: A Strategic Roadmap”, Intel Developer Forum, September 2004.

[8] Juling, W., “HPC System for Universities in Baden-Wurttemburg”, T-systems HPCN Workshop, Braunschweig, April 2004.

[9] Clabes, J. et al., “Design and Implementation of the POWER5 Microprocessor”, Proceeedings of the ACM/IEEE Design Automation Conference, June 2004.

[10] McCormick, J. and Knies, A., “A Brief Analysis of the SPEC CPU2000 Benchmarks on the Intel Itanium 2 Processor”, Technical Digest, Hot Chips 2002, August 2002.

[11] Preston, R. et al., “Design of an 8-wide Superscalar RISC Microprocessor with Simultaneous Multithreading”, Digest of Technical Papers, 2002 IEEE International Solid-State Circuits Conference, p. 334.

[12] Funk, M., “Simultaneous Multi-threading (SMT) on eServer iSeries POWER5 Processors”, IBM Corporation, May 2004.

[13] “IBM eServer P5 Virtualization Performance Considerations”, Draft Redbook, IBM Corporation, August 24, 2004.


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