someone wrote:
> "thick oxide device" supports up to 1.8 V.

Okay, I tried to look up what "thick" actually means. Texas Instruments talks about 5 V logic in :
> Input voltages greater than 7 V must be avoided to preclude damage to the gate oxide of
> the input stage. This damage is not necessarily permanent, but will adversely affect the
> expected lifetime of the circuit. The gate oxide of AHC devices is only 200 Å thick. An
> input voltage of 7 V corresponds to a field strength over the gate oxide of 350 kV/cm.
> Although breakdown of the oxide is expected only at input voltages above 10 V, electrons
> tunnel increasingly into the gate oxide at field strengths greater than 350 kV/cm,
> influencing characteristics of the transistors and causing failure.

Scaling down the nominal 5 V to 1.8 V gives a thickness of 7.2 nm.

So "thick" is about 35 Si atoms.

"The electronic structure at the atomic scale of ultrathin gate oxides" says:
> [...] The spatial extent of these states places a fundamental limit of 0.7nm (four
> silicon atoms across) on the thinnest usable silicon dioxide gate dielectric. And
> for present-day oxide growth techniques, interface roughness will raise this limit
> to 1.2nm.
> [...] a practical alternative to SiO2 (or its nitrogenated derivatives), providing
> a higher dielectric constant or a reduced leakage current, has not been identified
> yet

That was 1999. Any improvements since then?