RISC-V - incompetitive instruction set compared to ARMv8

By: j (invalid.delete@this.example.net),
Room: Moderated Discussions
Adrian (a.delete@this.acm.org) on November 2, 2019 9:33 am wrote:
> I refuse to believe to believe that instruction-pair fusion is simpler or better than the
> trivial enhancement of the instruction encoding to cover the more complex instructions that
> are needed in almost all loops, e.g. either with indexed or auto-indexed addressing.
>
>

OTOH risc-v has compare-and-branch instructions so it doesn't need to fuse compare+jump, nor does it have a flags register. At least the risc-v people are claiming that virtualizing the flags register is a somewhat complex task for superscalar/OoO implementations.

(the biggest downside afaics is that because the jump instructions need two register specifiers, so the max jump offset is quite small)
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    RISC-V - incompetitive instruction set compared to ARMv8Heikki Kultala
      RISC-V - incompetitive instruction set compared to ARMv8Ronald Maas
        RISC-V - incompetitive instruction set compared to ARMv8Ronald Maas
          RISC-V - incompetitive instruction set compared to ARMv8Michael S
        RISC-V - incompetitive instruction set compared to ARMv8Adrian
          RISC-V - incompetitive instruction set compared to ARMv8anon
            RISC-V - incompetitive instruction set compared to ARMv8Wilco
              RISC-V - incompetitive instruction set compared to ARMv8anon
              RISC-V - incompetitive instruction set compared to ARMv8Ronald Maas
                RISC-V - incompetitive instruction set compared to ARMv8anon
                  RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto
                    RISC-V - incompetitive instruction set compared to ARMv8anon
                      RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto
                        RISC-V - incompetitive instruction set compared to ARMv8Michael S
                    RISC-V - incompetitive instruction set compared to ARMv8David Hess
                      RISC-V - incompetitive instruction set compared to ARMv8rwessel
                        RISC-V - incompetitive instruction set compared to ARMv8David Hess
                RISC-V - incompetitive instruction set compared to ARMv8Wilco
                  RISC-V - incompetitive instruction set compared to ARMv8Ronald Maas
                    RISC-V - incompetitive instruction set compared to ARMv8Wilco
                      RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto
                      RISC-V - incompetitive instruction set compared to ARMv8R
                RISC-V - incompetitive instruction set compared to ARMv8sylt
                  RISC-V - incompetitive instruction set compared to ARMv8l
            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto
              The RISC-V bitmanip ISA extension has conditional movesWilco
                The RISC-V bitmanip ISA extension has conditional movesLinus Torvalds
                The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto
                  The RISC-V bitmanip ISA extension has conditional movesnone
                    The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto
                      The RISC-V bitmanip ISA extension has conditional movesnone
                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto
                          The RISC-V bitmanip ISA extension has conditional movesnone
                            I'm glad you're not that blind :) (NT)none
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto
                          The RISC-V bitmanip ISA extension has conditional movesMaynard Handley
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto
                              The RISC-V bitmanip ISA extension has conditional movesAdrian
                                The RISC-V bitmanip ISA extension has conditional movesRonald Maas
                                  The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto
                                    The RISC-V bitmanip ISA extension has conditional movesdmcq
                                    The RISC-V bitmanip ISA extension has conditional movesKonrad Schwarz
                                      The RISC-V bitmanip ISA extension has conditional movesnone
                                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto
                      The RISC-V bitmanip ISA extension has conditional movesanon
                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto
                          The RISC-V bitmanip ISA extension has conditional movesanon
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto
                              The RISC-V bitmanip ISA extension has conditional movesnone
                                RISC-V - incompetitive instruction set compared to ARMv8Ronald Maas
                                  RISC-V - incompetitive instruction set compared to ARMv8anonymou5
                                    The RISC-V bitmanip ISA extension has conditional movesRonald Maas
                                      The RISC-V bitmanip ISA extension has conditional movesnone
                                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto
                                      The RISC-V bitmanip ISA extension has conditional movesAdrian
                                        The RISC-V bitmanip ISA extension has conditional movesAdrian
                                        The RISC-V bitmanip ISA extension has conditional movesnone
                                          The RISC-V bitmanip ISA extension has conditional movesAdrian
                                      The RISC-V bitmanip ISA extension has conditional movesdmcq
                                      The RISC-V bitmanip ISA extension has conditional movesnoko
                                        The RISC-V bitmanip ISA extension has conditional movesRonald Maas
                              The RISC-V bitmanip ISA extension has conditional movesj
                          The RISC-V bitmanip ISA extension has conditional movesdmcq
                          The RISC-V bitmanip ISA extension has conditional movesMaynard Handley
                      The RISC-V bitmanip ISA extension has conditional movesAnon
                        RISC-V - incompetitive instruction set compared to ARMv8Ronal
          RISC-V - incompetitive instruction set compared to ARMv8dmcq
          RISC-V - incompetitive instruction set compared to ARMv8lockederboss
          RISC-V - incompetitive instruction set compared to ARMv8j
            RISC-V - incompetitive instruction set compared to ARMv8anon
              RISC-V - incompetitive instruction set compared to ARMv8j
                RISC-V - incompetitive instruction set compared to ARMv8Michael S
                  RISC-V - incompetitive instruction set compared to ARMv8none
                    RISC-V - incompetitive instruction set compared to ARMv8anon
                      RISC-V - incompetitive instruction set compared to ARMv8Adrian
                      RISC-V - incompetitive instruction set compared to ARMv8Michael S
                        RISC-V - incompetitive instruction set compared to ARMv8Linus Torvalds
                          RISC-V - incompetitive instruction set compared to ARMv8David Hess
                          RISC-V - incompetitive instruction set compared to ARMv8Michael S
                            RISC-V - incompetitive instruction set compared to ARMv8Linus Torvalds
                Flags RegisterDavid Hess
                  Flags RegisterWilco
                    Flags RegisterMaynard Handley
                    Flags RegisterDavid Hess
                      Flags RegisterWilco
                        Flags RegisterMegol
                          Flags RegisterMaynard Handley
          RISC-V - instruction fusionAnon
      RISC-V - incompetitive instruction set compared to ARMv8David Hess
        RISC-V - incompetitive instruction set compared to ARMv8Michael S
          RISC-V - incompetitive instruction set compared to ARMv8David Hess
            RISC-V - incompetitive instruction set compared to ARMv8Michael S
              RISC-V - incompetitive instruction set compared to ARMv8David Hess
                RISC-V - incompetitive instruction set compared to ARMv8anon.1
                  RISC-V - incompetitive instruction set compared to ARMv8Linus Torvalds
                    RISC-V - incompetitive instruction set compared to ARMv8anon.1
                      RISC-V - incompetitive instruction set compared to ARMv8Doug S
                        RISC-V - incompetitive instruction set compared to ARMv8David Hess
                          RISC-V - incompetitive instruction set compared to ARMv8Maynard Handley
                            RISC-V - incompetitive instruction set compared to ARMv8j
                          RISC-V - incompetitive instruction set compared to ARMv8TREZA
                            RISC-V - incompetitive instruction set compared to ARMv8David Hess
                              RISC-V - incompetitive instruction set compared to ARMv8Maynard Handley
                                RISC-V - incompetitive instruction set compared to ARMv8none
                        RISC-V - incompetitive instruction set compared to ARMv8anon.1
                          The RISC-V bitmanip ISA extension has conditional movesRonald Maas
                            Both are excellent ISAs ?Michael S
                            The RISC-V bitmanip ISA extension has conditional movesdmcq
                              The RISC-V bitmanip ISA extension has conditional movesRonald Maas
                            The RISC-V bitmanip ISA extension has conditional movesAdrian
                              The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto
                            The RISC-V bitmanip ISA extension has conditional movesanon.1
                              The RISC-V bitmanip ISA extension has conditional movesBrett
                                The RISC-V bitmanip ISA extension has conditional movesanon.1
                                  The RISC-V bitmanip ISA extension has conditional movesBrett
                                    The RISC-V bitmanip ISA extension has conditional movesMaynard Handley
                                    The RISC-V bitmanip ISA extension has conditional movesDavid Hess
                                      The RISC-V bitmanip ISA extension has conditional movesanon.1
                      RISC-V - incompetitive instruction set compared to ARMv8G. Boniface
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                          Op fusion and superscalar execution do NOT share same hardwareRonald Maas
                            Op fusion and superscalar execution do NOT share same hardwareanon
                            Op fusion and superscalar execution do NOT share same hardwareWilco
                            Op fusion and superscalar execution do NOT share same hardwareFoo_
                              Op fusion and superscalar execution do NOT share same hardwareanon.1
                    RISC-V - incompetitive instruction set compared to ARMv8wumpus
              RISC-V - conditional branches are problematic tooWilco
                reg-reg branchesMichael S
                  reg-reg branchesWilco
      RISC-V - incompetitive instruction set compared to ARMv8Montaray Jack
        RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto
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